1. Field of the Invention
The present invention relates to a delay locked loop (hereinafter, referred to as “DLL”) having a phase comparator, and more particularly to a DLL having a phase comparator including a shift register controller for controlling a shift register of a delay line, for performing fast phase locking and phase tracking.
2. Description of the Background Art
In general, a DLL is a circuit for controlling external output timing of data of a dynamic random access memory (hereinafter, referred to as “DRAM”) in response to an external clock signal inputted from the outside of the DRAM. In order to transmit the data to a chipset without an error, the DRAM and the chipset must be synchronized with the clock signal.
That is, when the external clock signal is inputted to the DRAM, a phase of the external clock signal is delayed by logic circuits such as a clock input buffer, a line loading and a data output buffer, and thus becomes different from a phase of an internal clock signal. The DLL is used to compensate for the phase difference.
The DLL compensates for the phase Clock Skew delayed by circuits inside of the DRAM, namely equalizes output timing of the data sensed in a DRAM core from the data output buffer to timing of the externally-inputted clock signal, so that the phase of the data outputted from the inside to the outside cannot be different from the phase of the clock signal.
FIG. 1 is a block diagram illustrating a general register controlled DLL.
The register controlled DLL includes first and second clock buffers 2 and 4, first and second delay lines 6 and 8, a dummy clock buffer 10, a divider 12, a phase comparator 14, a delay controller 16, a dummy delay line 18 and a replica circuit 20.
The first and second clock buffers 2 and 4 respectively output a rising internal clock signal RCLK synchronized with a rising edge of an external clock signal CLK and a falling internal clock signal FCLK synchronized with a falling edge of the external clock signal CLK, in response to the external clock signal CLK and a clock signal CLKB having the opposite phase to the external clock signal CLK.
The first and second delay lines 6 and 8 respectively delay phases of the internal clock signals RCLK and FCLK from the first and second clock buffers 2 and 4. Here, the delay lines 6, 8 and 18 are formed by connecting a plurality of unit delay cells having NAND gates in series. Signals for controlling each unit delay cell correspond to signals outputted from a shift register one by one. The clock signal is transmitted to the unit delay cell for which a value of an output terminal of the shift register is a high level, to form a delay path.
The dummy clock buffer 10 buffers the external clock signal CLK and outputs the internal clock signal.
The divider 12 divides a frequency of the internal clock signal from the dummy clock buffer 10 by a specific divider ratio (1/N) for low power consumption. Here, N is a positive number and generally 8 or 4.
The phase comparator 14 compares the phase of the input clock signal with the phase of the output clock signal, and detects phase difference between the two clock signals. Here, the phase comparator 14 compares a phase of a reference clock signal REC divided by the divider 12 with a phase of a clock signal FBC fed back through the inside circuits of the DLL.
The delay controller 16 includes a logic circuit for deciding an input path of the delay lines 6, 8 and 18 and a bi-directional shift register. The delay controller 16 controls delay rates of the first and second delay lines 6 and 8 and the dummy delay line 18 in response to the output signal from the phase comparator 14.
The dummy delay line 18 has the same structure as the first and second delay lines 6 and 8, and delays the phase of the divided reference clock signal REC.
The replica circuit 20 includes modeling circuits of delay elements until the clock signal inputted from the outside of the chip is outputted to the delay line and the clock signal outputted from the delay line is outputted to the outside of the chip.
In order to synchronize the phases of the external clock signal and the internal clock signal, the phase comparator 14 compares the two clock signals in the real time.
The phase comparator 14 provides phase information of the two clock signals to the delay controller 16 (shift register array) to control the delay rates of the delay lines 6, 8 and 18, and thus decreases the phase difference.
The phase comparator 14 divides the state of the external clock signal and the internal clock signal into lead, lag, lock, lead more than long delay and lag more than long delay. Here, the long delay of the lead more than long delay or lag more than long delay state is identical to the delay time of the unit delay cells of the delay lines 6, 8 and 18 corresponding to the divider ratio of the divider 12. The divider ratio of the divider 12 is 8, and thus the long delay is the delay time by 8 unit delay cells.
The delay controller 16 outputs signals for controlling the delay lines 6, 8 and 18 depending on the five states. In the lead state, the delay controller 16 generates a shift left signal, and in the lag state, the delay controller 16 generates one shift right signal, in one period of the two clock signals.
In the lock state, the delay controller 16 does not generate shift signals, and in the lead more than long delay or lag more than long delay state, the delay controller 16 controls the shift operation in response to the non-divided clock signal in one comparison period of the two divided clock signals.
FIG. 2 is a detailed circuit diagram illustrating the conventional phase comparator.
The phase comparator includes a comparing unit 22 for comparing the phase of the reference clock signal REC obtained by dividing a dummy clock signal outputted from the dummy clock buffer 10 by the divider 12 with the phase of the feedback clock signal FBC, and a shift register control unit 24 for controlling the delay controller 16 having the shift register for controlling the delay time of the delay lines 6, 8 and 18 in response to the data from the comparing unit 22.
The comparing unit 22 is comprised of first and second unit comparing units 26a and 26b for detecting the normal lead state and the normal lag state, third and fourth unit comparing units 26c and 26d for detecting the lead more than long delay state and the lag more than long delay state, a first logic unit 28 for logically combining the reference clock signal REC and the feedback clock signal FBC, a second logic unit 30 for logically combining the output signals PC1˜PC4 from the first and second unit comparing units 26a and 26b, a third logic unit 32 for logically combining the output signals A17 and A2 from the third and fourth unit comparing units 26c and 26d, and a fourth logic unit 34 for logically combining the output signal from the third logic unit 32, the signal obtained by inverting the phase of the signal outputted from the first logic unit 28 by an inverter, and the driver clock signal RCLKDLL outputted from the first delay line 6 through a driver. Here, the third unit comparing unit 26c includes a second delay unit 36b having the same delay time for delaying the phase of the feedback clock signal FBC as the delay time by the unit delay cells of the delay lines 6, 8 and 18 corresponding to the divider ratio of the divider 12, the fourth unit comparing unit 26d includes a third delay unit 36c having the same delay time for delaying the phase of the reference clock signal REC as the delay time by the unit delay cells of the delay lines 6, 8 and 18 corresponding to the divider ratio of the divider 12, and the second unit comparing unit 26b includes a first delay unit 36a having the shorter delay time for delaying the phase of the feedback clock signal FBC than the other delay units 36b and 36c. 
The shift register control unit 24 includes a T flip-flop 38 synchronized with the accelerating control signal AC from the fourth logic unit 34, and a fifth logic unit 40 for logically combining signals L1 and L2 outputted from the second logic unit 30, and the output signals M1 and M2 from the T flip-flop 38, and outputting shift right signals SR1 and SR2 and shift left signals SL1 and SL2.
The comparing unit 22 compares the phases of the reference clock signal REC and the feedback clock signal FBC, and divides the comparison result into five states. Here, the five states are normal lead, normal lag, lock, lead more than long delay and lag more than long delay.
Accordingly, the shift register control unit 24 sets and outputs different state combinations of the shift right signals SR1 and SR2 and the shift left signals SL1 and SL2 depending on the five states which are output results from the comparing unit 22. In the lock state, the shift register control unit 24 does not generate the shift signals.
FIGS. 3a to 3d are timing diagrams illustrating the operation of the conventional phase comparator of FIG. 2 depending on the four states except the lock state.
FIG. 3a is a timing diagram of the operation signals when the result of the phase comparator of FIG. 2 is the normal lead state.
The accelerating control signal AC has a low level, and thus one shift operation is performed in one period of the divided clock signals REC and FBC. That is, the first shift right signal SR1 maintains a high level in one period of the divided clock signals REC and FBC, and the second shift right signal SR2 maintains a high level in one period of the divided clock signals REC and FBC. Here, the shift left signals SL1 and SL2 maintain a low level.
FIG. 3b is a timing diagram of the operation signals when the result of the phase comparator of FIG. 2 is the normal lag state.
The accelerating control signal AC has a low level, and thus one shift operation is performed in one period of the divided clock signals REC and FBC. That is, the first shift left signal SL1 maintains a high level in one period of the divided clock signals REC and FBC, and the second shift left signal SL2 maintains a high level in one period of the divided clock signals REC and FBC. Here, the shift right signals SR1 and SR2 maintain a low level.
FIG. 3c is a timing diagram of the operation signals when the result of the phase comparator of FIG. 2 is the lead more than long delay state.
The accelerating control signal AC has a high level, and thus the shift operation is performed in response to the non-divided rising clock signal RCLK in one period of the divided clock signals REC and FBC. That is, the first shift right signal SR1 and the second shift right signal SR2 alternately have a high level at every rising edge of the external clock signal ECLK. Here, the shift left signals SL1 and SL2 maintain a low level.
FIG. 3d is a timing diagram of the operation signals when the result of the phase comparator of FIG. 2 is the lag more than long delay state.
The accelerating control signal AC has a high level, and thus the shift operation is performed in response to the non-divided rising clock signal RCLK in one period of the divided clock signals REC and FBC. That is, the first shift left signal SL1 and the second shift left signal SL2 alternately have a high level at every rising edge of the external clock signal ECLK. Here, the shift right signals SR1 and SR2 maintain a low level.
In the conventional DLL, the clock signal used for fast phase locking is the clock signal generated depending on the rising edge. The shift operation is performed for the one period of the clock signal in response to the non-divided clock signal. However, the clock signal generated depending on the falling edge is not used for the shift operation, which increases the phase lock time. It is also impossible to compensate for tracking due to phase variations by noises.